1. Field of the Invention
The present invention relates to the production of circuit boards having circuitry on both sides of the board and providing connections therebetween by the use of conductive metal-filled holes. More particularly, the present invention is directed to the production of very fine line circuits of this nature.
2. Description of the Prior Art
There is a definite need in the art for small size circuit boards due to the tendency of the industry to miniaturize as much as possible. However, this presents a significant problem in the production of the circuit boards since conventional masking and plating procedures are not amenable to the production of very fine or narrow conductors.
One method of overcoming this size limitation is to produce circuit boards with circuitry on both sides, and thus allow a single board to carry more components. In order to do this, it is necessary to provide continuity between the two surfaces of the particular board. Such continuity may be provided by the production of a board with plugs of conductive metal in holes manufactured in the board. U.S. Pat. No. 3,566,005 to Shaheen describes such a circuit board with plugs and welding contacts.
Additionally, Ryan in U.S. Pat. No. 3,606,677 discloses a system in which the base material is sensitized after being drilled to provide the connections, and then electroless plated. A mask is then applied and electroplating effected in the unmasked areas. The mask is then removed and the electroless plate flash etched. The resulting circuit, however, suffers from the normal disabilities of this type of circuit, in that the masking and plating processes do not allow for very fine line circuit production. Another very similar process is described in U.S. Pat. No. 4,104,111 of Mack. This system uses the early masking process, noted above, but adds multiple plating steps including solder plating. This process, like the Ryan process, does not allow for the plating of very small holes, and is further limited to systems where the surface plating is approximately the same thickness as the plating of the hole. Thus further disabilities exist when considering miniaturization, since the plating thicknesses are dependent on each other.
Further, Hauser et al in U.S. Pat. No. 2,872,391 discloses a basic concept utilizing a strippable film over a background. In the Hauser et al system, the strippable film is layered over a base that has been previously coated with foil and a resist. The strippable film is removable without disturbing the resist, and holes are drilled in areas not covered by the film. The hole walls are then coated with a conductive material such as metal or graphite, and the film stripped away. This system allows hole plating at this time because the resist has been exposed again. However, the system depends on multi-layered patterns and resists, and uses the standard system, noted above, once the strippable film has been removed.
The above processes along with others in the art have come to be known as subtractive and additive processes. The subtractive process is more commonly employed, and includes the above systems in which copper cladding is applied to the substrate prior to copper electroplating, followed by the application of the photoresist, exposure and etching.
In the additive process, for example as described in the Ryan U.S. Pat. (No. 3,606,677) above, the circuitry is applied over the unclad substrate and then plating is effected in the area defined by the portions of the substrate not covered by photoresist. The inherent problem of the additive process is the lack of adhesion between the substrate and the plating. It has been suggested that this plating can produce sufficient adhesive strength, equal to that produced by foil lamination, but this is not generally accepted by the industry or by the armed forces.
It can thus be seen that each of the above-described processes of manufacturing circuit boards has certain inherent advantages and disadvantages. As a result, a continuous effort is being made to achieve better high-density packaging of electronic components. This requires the achievement of a reduction in conductor line width and concurrently of the space between conductors while maintaining good adhesion between the substrate and the printed circuits thereon. It is this improvement that is attained by the present invention.